
`timescale 1ns / 1ps

module decoder_3_8(
	input  wire [2:0] in,
	output wire [7:0] out
	);

genvar i;
generate for(i=0; i<8; i=i+1) begin : gen_for_dec_3_8
	assign out[i] = (in == i);
end endgenerate
endmodule



module decoder_5_32(
	input  wire [ 4:0] in,
	output wire [31:0] out
	);

genvar i;
generate for(i=0; i<32; i=i+1) begin : gen_for_dec_5_32
	assign out[i] = (in == i);
end endgenerate
endmodule




module decoder_6_64(
	input  wire [ 5:0] in,
	output wire [63:0] out
	);

genvar i;
generate for(i=0; i<64; i=i+1) begin : gen_for_dec_6_64
	assign out[i] = (in == i);
end endgenerate
endmodule




module decoder_7_128(
	input  wire [  6:0] in,
	output wire [127:0] out
	);

genvar i;
generate for(i=0; i<128; i=i+1) begin : gen_for_dec_7_128
	assign out[i] = (in == i);
end endgenerate
endmodule
